The present invention relates generally to chemical mechanical polishing of substrates, and more particularly to a carrier head for a chemical mechanical polishing apparatus.
Integrated circuits are typically formed on substrates, particularly silicon wafers, by the sequential deposition of conductive, semiconductive or insulative layers. After each layer is deposited, it is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the outer or uppermost surface of the substrate, i.e., the exposed surface of the substrate, becomes increasingly non-planar. This non-planar surface presents problems in the photolithographic steps of the integrated circuit fabrication process. Therefore, there is a need to periodically planarize the substrate surface.
Chemical mechanical polishing (CMP) is one accepted method of planarization. This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a rotating polishing pad. The polishing pad may be either a “standard” or a fixed-abrasive pad. A standard polishing pad has durable roughened surface, whereas a fixed-abrasive pad has abrasive particles held in a containment media. The carrier head provides a controllable load, i.e., pressure, on the substrate to push it against the polishing pad. A polishing slurry, including at least one chemically-reactive agent, and abrasive particles, if a standard pad is used, is supplied to the surface of the polishing pad.
The effectiveness of a CMP process may be measured by its polishing rate, and by the resulting finish (absence of small-scale roughness) and flatness (absence of large-scale topography) of the substrate surface. The polishing rate, finish and flatness are determined by the pad and slurry combination, the relative speed between the substrate and pad, and the force pressing the substrate against the pad.
A reoccurring problem in CMP is the so-called “edge-effect”, i.e., the tendency of the edge of the substrate to be polished at a different rate than the center of the substrate. The edge effect typically results in over-polishing (the removal of too much material from the substrate) at the substrate perimeter, e.g., the outermost five to ten millimeters of a 200 mm wafer. Over-polishing reduces the overall flatness of the substrate, causing the edge of the substrate to be unsuitable for integrated circuit fabrication and decreasing the process yield.